Setting Examples For 1280X720P; External Clock And Clamp Mode Operation; Introduction To External Clock And Clamp Mode - Analog Devices Advantiv ADV7604 Hardware Manual

AUTO_SL_FILTER_FREEZE_EN, CP Map, Address 0xCB, [5]
This bit determines if the internally generated parameter for the position of the HSync trailing edge
is updated during the VBI region. This control is only intended for auto-graphics mode. It is
recommended to leave AUTO_SL_FILTER_FREEZE_EN to default. Unless
AUTO_SL_FILTER_FREEZE_EN is left to default, the part may generate an incorrect HSync
trailing edge position parameter if the input synchronization is embedded and has serration pulses.
Function
AUTO_SL_FILTER_FREE
ZE_EN
0
1

10.15.4 Setting Examples for 1280x720p

The section provides settings examples for a video input with resolution 1280x720p.
The PLL divide ratio should be set to 1650 decimal.
If CP_START_SAV = 0x000, CP_START_EAV = 0x5DC, CP_START_VBI = 0x2E9, and
CP_END_VBI = 0x00, then:
• SAV will be at pixel 309 (18.75% of 1650 − the PLL divide ratio value)
• EAV will be at pixel 1500 because CP_START_EAV is set to 0x5DC (= 1500 decimal)
• VBI will start on line 745 because CP_START_VBI is set to 0x2E9 (= 745 decimal)
• VBI will end on line 4 because CP_END_VBI is set to 0x00 so the automatic value is used

10.16 External Clock and Clamp Mode Operation

10.16.1 Introduction to External Clock and Clamp Mode

The ADV7604 allows the user to control ADC sampling and clamping externally by providing the
ADC sampling clock (external clock) and the clamp pulse externally.
In this external clock and clamp mode, system delay may need to be compensated for between the
ADV7604 and the external control device that feeds the external clock and clamp pulse signals, as
shown in Figure 106.
A system delay can exist between the ADV7604 and the external control device providing clock
and clamp signals, as depicted in
mode to compensate for this system delay.
Rev. F August 2010
Description
Does not freeze trailing edge position of HSync during VBI
region
Freezes trailing edge position of HSync during VBI region
Figure 106. The ADV7604 provides an optional regeneration
312
ADV7604