Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 151

SDRAM power-up sequence start.
the power-up mode and the
ization) sequence. When this bit is set (=1), the SDRAM power-up
sequence starts on the next SDRAM access. When cleared, this bit has no
effect. This bit always reads zero. See also
page 3-64.
SDRAM self-refresh command.
self-refresh mode. When cleared (=0) this bit has no effect. This bit always
reads zero. In self-refresh mode, the SDRAM performs refresh operations
internally which reduces the SDRAM's power consumption.
When is set to 1, the SDC enters an idle state. In this state, it issues
SDSRF
a precharge command (if necessary) and then issues a self-refresh com-
mand. If an internal access is pending, the SDC delays issuing the
self-refresh command until it completes all pending SDRAM access
requests. Once the SDRAM device enters into self-refresh mode, the
SDRAM controller asserts the
ister ( ). The SDRAM controller ignores other self-refresh requests
SDSTAT
when the SDRAM device is already in self-refresh mode.
The SDRAM device exits self-refresh mode only when the SDC
receives a request for SDRAM space access. There is no way to can-
cel entry into self-refresh mode.
SDRAM external data path width.
SDRAM interface is 32 or 16 bits wide.
• If set (=1), a 16-bit SDRAM should be used;
DATA[15–0]
ADDR[14:0]
16 to 32-bit packing is performed.
Note that
page 3-53
ADSP-21368 SHARC Processor Hardware Reference
bit starts an SDRAM power-up (initial-
SDPSS
SDSRF
SDSRA
should be connected to the SDRAM data pins;
should be connected to SDRAM address pins 14–0;
pins are also used. See tables
ADDR[18:17]
to Table 3-25 on page 3-57
bit 14. The
SDPSS
"Load Mode Register" on
bit 15. When set (=1), starts the
bit in the SDRAM control status reg-
bit 16. Selects whether the
X16DE
for bank address usage.
External Port
bit specifies
SDPM
Table 3-22 on
3-43