Uartxmode Register; I/O Mode - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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Table of Contents

For information on UART DMA registers, see

UARTxMODE Register

The UART mode register controls miscellaneous settings such as packing

and address detection.

TxMODE)" on page A-126.

In I/O mode, data is moved to and from the UART by the processor core.

To transmit a character, load it into the

can be read from the

one character at time.

To prevent any loss of data and misalignments of the serial data stream,

the UART line status register (

handshaking—

and cleared when the processor loads new data into the

Writing this register when it is not empty overwrites the register with the

new value and the previous character is never transmitted.

flag signals when new data is available in the

ter. This flag is cleared automatically when the processor reads from this

viously received value. When the

newly received data overwrites the

) flag is set.

With interrupts disabled, these status flags can be polled to determine

when data is ready to move. Note that because polling is processor-inten-

sive, it is not typically used in real-time signal processing environments.

ADSP-21368 SHARC Processor Hardware Reference

For more information, see "Mode Registers (UAR-

flag is set when the

UART Port Controller

"UART DMA" on

) provides two status flags for

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