Register Descriptions; Twi Master Internal Time Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Register Descriptions

The clock generation module is used to generate an external serial clock
( ) when in master mode. It includes the logic necessary for synchroni-
SCL
zation in a multimaster clock configuration and clock stretching when
configured in slave mode.
Register Descriptions
The TWI controller has 16 registers which are described in the following
sections. More information on these registers can be found in
Interface Registers" on page

TWI Master Internal Time Register

The TWI control register (
well as to establish a relationship between the peripheral clock (
the TWI controller's internally-timed events. The internal time reference
is derived from
PRESCALE = f
Additional information for the
TWI Enable (
TWIEN
tion. It is recommended that this bit be set and remain set at the time
is initialized. This guarantees accurate operation of bus busy
PRESCALE
detection logic.
Prescale (
PRESCALE
clock periods that equals the time period corresponding to a 10 MHz fre-
quency. This number is represented as a 7-bit binary value.
12-4
A-130.
TWIMITR
using a prescaled value.
PCLK
/10 MHz
PCLK
TWIMITR
). This bit must be set for slave or master mode opera-
). This value should be set to the number of peripheral
ADSP-21368 SHARC Processor Hardware Reference
) is used to enable the TWI module as
register bits includes:
"Two Wire
) and
PCLK