Index - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

I

INDEX

Numerics
128-channel TDM, 5-4
16-bit to 32-bit word packing enable
(PACK), 5-62
16-bit word lengths, 5-45, 6-32,
32-bit word lengths, 5-45, 6-32,
8-bit word lengths, 6-31
A
accessing IOP registers, latency in,
accuracy, PWM, 8-17
ACK (acknowledge) signal, 3-2, 3-19,
acknowledge (ACK) pin,
activate command, bank,
active low frame sync select for frame sync
(INVFSx) bit, 13-12
active low versus active high frame syncs,
5-39
active state multichannel receive frame sync
select (LMFS) bit,
AD1855 stereo DAC
power down, 6-7
address
column, row and bank address mapping
(32-bit), 3-53
core to external memory,
decoding address bank,
row in SDRAM, 3-34
SDRAM (external memory space),
SPORT IOP (listing),
address bus (ADDR) pin, 3-20,
ADSP-21368 SHARC Processor Hardware Reference
7-14
7-14
2-3
3-21
3-20
3-31
5-29
3-52
3-53
3-52
5-50
3-83
addressing, 14-53
7-bit in TWI, 12-1,
general call in TWI,
IOP, 2-29
pre-modify, 2-39
restrictions on external memory,
transfer phase in TWI,
AMI
See also external port, SDRAM
controller, shared memory
ADDR23-0 bits, 3-28
control (AMICTLx) register, 3-25,
to A-19
DMA, 3-20
hold cycles, 3-23
idle cycle, 3-22
memory bank support,
modes, setting, 3-24
most significant word first (MSWF) bit,
3-25
packing data (PKDIS) bit,
read/write throughput,
reading external memory,
receive (AMIRX) register,
signals, 3-20
status (AMISTAT) register,
unpacking data, 3-27
wait states, 3-21
writing external memory,
12-15
12-14
3-3
12-6
A-17
3-28
3-25
3-28
3-25
3-25
A-20
3-26
I-1