Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 152

SDRAM Controller
• If cleared (=0), a 32-bit SDRAM should be used;
DATA[31–0]
ADDR[15:1]
more information, see "SDRAM Address Mapping" on page 3-51.
Note that
page 3-53
SDRAM tWR parameter setting.
delay, in number of
command (drives write data) and a precharge command.
The t parameter enables applications to accommodate the SDRAM's
WR
timing requirements.
ory Accesses" on page 3-36.
be selected as shown in
Table 3-17. SDRAM t
SDTWR Bit Setting
00
SDTWR1 = 01
SDTWR2 = 10
SDTWR3 = 11
SDRAM optional refresh.
SDRAM in FPGAs. When set (=1), auto-refresh is not performed and the
bit does not have any effect. When cleared (=0), auto-refresh
Force AR
occurs when the refresh counter expires. See also
Control Register (SDRRC)" on page
3-44
should be connected to the SDRAM data pins;
should be connected SDRAM address pins 14–0.
pins are also used. See tables
ADDR[18:17]
to Table 3-25 on page 3-57
SDTWR
cycles, between the time the SDC issues a write
SDCLK
≥
SDTWR
For more information, see "Timing External Mem-
Any value between 1 and 3
Table 3-17.
Bit Settings
WR
SDRAM Parameter Setting
Reserved
One clock cycle
Two clock cycles
Three clock cycles
bit 19. Used for memories built as
SDORF
ADSP-21368 SHARC Processor Hardware Reference
for bank address usage.
bits 18–17. Defines the required
t
WRmin
----------------- -
t
SDCLK
"SDRAM Refresh Rate
3-49.
For
Table 3-22 on
cycles may
SDCLK