Sport Transmit Buffer Registers (Txspx - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Table A-9. SPMCTLx Register Bit Descriptions (Cont'd)
Bit Name
22–16 CHNL
23 MCEB
27–24 DMASxy
31–28 DMACHSxy

SPORT Transmit Buffer Registers (TXSPx)

The addresses of the
TXSP0A – 0xC60
TXSP1A – 0xC64
TXSP2A – 0x460
TXSP3A – 0x464
TXSP4A – 0x860
TXSP5A – 0x864
TXSP6A – 0x4860
TXSP7A – 0x4864
The 32-bit
TXSPx
operations. The reset value for these registers is undefined. For more
information on how transmit buffers work, see
Data Buffers (TXSPxA/B, RXSPxA/B)" on page
ADSP-21368 SHARC Processor Hardware Reference
Description
Current Channel Selected (read-only, sticky). Identify the cur-
rently selected transmit channel slot (0 to 127).
Multichannel Enable, B Channels.
0 = Disable
1 = Enable
DMA Status. Selects the transfer status.
0 = Inactive
1 = Active
(read-only)
DMA Chaining Status.
0 = Inactive
1 = Active
(read-only)
registers are:
TXSPx
TXSP0B – 0xC62
TXSP1B – 0xC66
TXSP2B – 0x462
TXSP3B – 0x466
TXSP4B – 0x862
TXSP5B – 0x866
TXSP6B – 0x4862
TXSP7B – 0x4866
registers hold the output data for serial port transmit
Register Reference
"Transmit and Receive
5-67.
A-43