Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 560

Programming Examples
2. Program the
values to be transmitted in the event the slave is addressed as a
transmitter. This is an optional step. If no data is written and the
slave is addressed and a transmit is required, the serial clock (
stretched and an interrupt is generated.
3. Program the
FIFO buffer interrupts should occur with each byte transmitted
(received) or with each 2 bytes transmitted (received).
4. Program the
desired interrupt sources. As an example, programming the value
0x000F results in an interrupt output to the processor when a valid
address match is detected, a valid slave transfer completes, a slave
transfer has an error, or a subsequent transfer has begun but the
previous transfer has not been serviced.
5. Program the
mode operation. As an example, programming the value 0x0005
enables slave mode operation, requires 7-bit addressing, and indi-
cates that data in the transmit FIFO buffer is intended for slave
mode transmission.
Table 12-2 shows what the interaction between the TWI controller and
the processor might look like when the slave is addressed as a receiver.
Table 12-2. Slave Mode Setup Interaction (Slave Addressed as Receiver)
TWI Controller Master
Interrupt: TWISINIT – Slave transfer has been
initiated.
Interrupt: TWIRXS – Receive buffer has 1 or 2
bytes (according to TWIRXINT).
...
Interrupt: TWISCOMP – Slave transfer com-
plete.
12-16
or
TXTWI8 TXTWI16
register. Indicate if transmit (or receive)
TWIFIFOCTL
register. Enable bits associated with the
TWIIMASK
register. This prepares and enables slave
TWISCTL
Processor
Acknowledge: Clear interrupt source bits.
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
...
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
ADSP-21368 SHARC Processor Hardware Reference
register. These are the initial data
) is
SCL