Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 854

Interrupt Registers
Table B-7. IMASKP Register Bit Descriptions (Cont'd)
Bit Name
6 BKPI
7 Reserved
8 IRQ2I
9 IRQ1I
10 IRQ0I
11 DAI1I
12 SPIAI
13 GPTMR0I
14 SP1I
B-24
Description
Hardware Breakpoint Interrupt. When the processor is servicing
another interrupt, this bit indicates if the BKPI interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0).
IRQ2 Hardware Interrupt. When the processor is servicing another
interrupt, this bit indicates if the IRQ2I interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0). An IRQ2I occurs when an exter-
nal device asserts the FLAG2 pin configured as IRQ2.
IRQ1 Hardware Interrupt. When the processor is servicing another
interrupt, this bit indicates if the IRQ1I interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0). An IRQ1I occurs when an exter-
nal device asserts the FLAG1 pin configured as IRQ1.
IRQ0 Hardware Interrupt. When the processor is servicing another
interrupt, this bit indicates if the IRQ0I interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0). An IRQ0I occurs when an exter-
nal device asserts the FLAG0 pin configured as IRQ0.
DAI High Priority Interrupt. When the processor is servicing another
interrupt, this bit indicates if the DAI1I interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0). This is the higher priority
option.
SPI Transmit or Receive High Priority Interrupt. When the processor
is servicing another interrupt, this bit indicates if the SPIAI interrupt is
unmasked (if set, = 1), or the SPIAI interrupt is masked (if cleared, = 0).
This is the higher priority option.
General-Purpose IOP Timer 0 Interrupt. When the processor is servic-
ing another interrupt, this bit indicates if the GPTMR0I interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0).
SPORT 1 Interrupt. When the processor is servicing another interrupt,
this bit indicates if the SP1I interrupt is unmasked (if set, = 1), or
masked (if cleared, = 0). An SP1I interrupt occurs two cycles after the
last bit of an input/output serial word is latched into/from
RXSP1A/TXSP1A, or RXSP1B/TXSP1B.
ADSP-21368 SHARC Processor Hardware Reference