Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 855

Table B-7. IMASKP Register Bit Descriptions (Cont'd)
Bit Name
15 SP3I
16 SP5I
17 Reserved
18 P15I
19 Reserved
20 CB7I
21 CB15I
22 TMZLI
23 FIXI
24 FLTOI
ADSP-21368 SHARC Processor Hardware Reference
Description
SPORT 3 Interrupt. When the processor is servicing another interrupt,
this bit indicates if the SP3I interrupt is unmasked (if set, = 1), or
masked (if cleared, = 0). An SP3I interrupt occurs two cycles after the
last bit of an input/output serial word is latched into/from
RXSP3A/TXSP3A, or RXSP3B/TXSP3B.
SPORT 5 Interrupt. When the processor is servicing another interrupt,
this bit indicates if the SP5I interrupt is unmasked (if set, = 1), or
masked (if cleared, = 0). An SP5I interrupt occurs two cycles after the
last bit of an input/output serial word is latched into/from
RXSP5A/TXSP5A, RXSP5B/TXSP5B.
Programmable Interrupt 15 (MTMDMA Interrupt).
DAG1 Circular Buffer 7 Overflow Interrupt. When the processor is
servicing another interrupt, this bit indicates if the CB7I interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0). A circular buffer
overflow occurs when the DAG circular buffering operation increments
the I register past the end of the buffer.
DAG2 Circular Buffer 15 Overflow Interrupt. When the processor is
servicing another interrupt, this bit indicates if the CB15I interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0). A circular buffer
overflow occurs when the DAG circular buffering operation increments
the I register past the end of the buffer.
Timer Expired (Low Priority) Interrupt. When the processor is servic-
ing another interrupt, this bit indicates if the TMZLI interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0).
tion, see "TMZHI" on page B-15.
Fixed-Point Overflow Interrupt. When the processor is servicing
another interrupt, this bit indicates if the FIXI interrupt is unmasked
(if set, = 1), or the FIXI interrupt is masked (if cleared, = 0).
Floating-Point Overflow Interrupt. When the processor is servicing
another interrupt, this bit indicates if the FLTOI interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0).
Interrupts
For more informa-
B-25