Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 577

CLO CK INPUT
(FOR BOTH CLOCK
AND FRAME SYNC)
CLOCK OUTPUT
FRAME SYNC OUTPUT
(PHASE SHIFT = PERIOD -1)
FRAME SYNC OUT PUT
(PHASE SHIFT = 0)
FRAME SYNC OUT PUT
(PHASE SHIFT = 1)
FRAME SYNC OUT PUT
(PHASE SHIFT = 2)
OTHER VALUES:
CLOCK DIVISOR = 4
F RAME SYNC DIVISOR = 16
PULSE WIDTH = 8
Figure 13-3. Phase Shift Settings
frame sync C is specified in the
and the pulse width of frame sync D is specified in the
of the
PCG_PW2
If the pulse width is equal to 0 or if the divisor is even, then the actual
pulse width of the frame sync output is equal to:
If the pulse width is equal to 0 or if the divisor is odd, then the actual
pulse width of the frame sync output is equal to:
ADSP-21368 SHARC Processor Hardware Reference
ENABLE
PWFSC
register.
FrameSyncDivisor
--------------------------------------------- -
=
Pulse Width
FrameSyncDivisor 1
------------------------------------------------------ -
=
Pulse Width
Precision Clock Generators
bits (15–0) of the
PWFSD
2
–
2
register
PCG_PW2
bits (31–16)
13-11