External Port Registers; External Port Control Register (Epctl - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

External Port Registers

Table A-2. System Status Register (SYSTAT) Bit Descriptions (Cont'd)
Bit Name
7 Reserved (reset value =0)
10–8 IDC
31-11 Reserved (reset value =0)
External Port Registers
The following registers are used to control asynchronous memory inter-
face (AMI), the SDRAM controller (SDC), and the shared memory
interface (ADSP-21368 only).

External Port Control Register (EPCTL)

The external port control register can be programmed to arbitrate the
accesses between the processor core and DMA, and between different
DMA channels. These registers are shown in
Table A-3.
A-10
Description
ID Code. These bits indicate the state of the ID pins on the proces-
sor. The reset value of IDC is undefined.
ADSP-21368 SHARC Processor Hardware Reference
Figure A-4 and described in