Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 360

Moving Data Between SPORTs and Internal Memory
Table 5-13. SPORT DMA Parameter Registers Addresses (Cont'd)
Register
CPSP6B
IISP7A
IMSP7A
CSP7A
CPSP7A
IISP7B
IMSP7B
CSP7B
CPSP7B
Reserved (0x850 to 0x85F)
When programming a SPORT channel (either A or B) as a transmitter,
only the corresponding
while the receive buffers (
when the SPORT channel A and B is programmed as a receiver, only the
corresponding
When performing core-driven transfers, write to the buffer designated by
the bit setting in the
SPTRAN
the SPORT logic performs the data transfer from internal memory
to/from the appropriate buffer depending on the
inactive SPORT data buffers are read or written to by the core while the
port is enabled, the core hangs. For example, if a SPORT is programmed
to be a transmitter, while at the same time the core reads from the receive
buffer of the same SPORT, the core hangs just as it would if it were read-
ing an empty buffer that is currently active. This locks up the core until
the SPORT is reset.
5-80
Address DMA Channel
0x4847 13
0x4848 14
0x4849 14
0x484A 14
0x484B 14
0x484C 15
0x484D 15
0x484E 15
0x484F 15
and
TXSPxA
RXSPxA
and
RXSP0A RXSP0B
SPCTLx
ADSP-21368 SHARC Processor Hardware Reference
SPORT Buffer
RXSP6B or TXSP6B
RXSP7A or TXSP7A
RXSP7A or TXSP7A
RXSP7A or TXSP7A
RXSP7A or TXSP7A
RXSP7B or TXSP7B
RXSP7B or TXSP7B
RXSP7B or TXSP7B
RXSP7B or TXSP7B
SPORT buffer becomes active,
TXSPxB
and ) remain inactive. Similarly,
RXSPxB
SPORT buffer is activated.
registers. For DMA-driven transfers,
SPTRAN
bit setting. If the