Shared Memory Interface Status - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

While the
BUSLK
bus mastership by executing a conditional instruction with the bus master
( ) or not bus master (
BM
IF NOT BM JUMP(PC,0); /* Wait for bus mastership */
If the processor becomes the bus master, it can proceed with the external
read or write. If not, it can clear its
A read-modify-write operation is accomplished with the following steps:
1. Request bus lock by setting the
2. Wait for bus mastership to be acquired.
3. Read the semaphore, test it, then write to it.
Locking the bus prevents other processors from writing to the semaphore
while the read-modify-write operation is occurring.

Shared Memory Interface Status

The system status (
and multiprocessor systems.
register.
Table 3-32. SYSTAT Register
Bit(s) Name
1 BSYN
6-4 CRBM
10-8 IDC
ADSP-21368 SHARC Processor Hardware Reference
bit is set, the processor can determine if it has acquired
) condition codes, for example:
Not BM
) register provides status information for host
SYSTAT
Table 3-32
Definition
Bus Synchronized. This bit indicates whether the proces-
sor's bus arbitration logic is synchronized (if set, =1) or is
not synchronized (if cleared, =0, reset value).
Current Bus Master. These bits indicate the ID of the
processor that is currently the bus master in a multipro-
cessor system.
ID Code. These bits indicate the state of the ID pins on
the processor.
bit and try again later.
BUSLK
bit in
BUSLK SYSCTL
shows the status bits in this
External Port
.
3-93