Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 534

UART Control and Status Registers
ZERO-FILLED RX9D1
31 24
Figure 11-3. Receive Buffer Register (Packing Enabled)
A sampling clock equal to 16 times the baud rate samples the data as close
to the midpoint of the bit as possible. Because the internal sample clock
may not exactly match the asynchronous receive data rate, the sampling
point drifts from the center of each bit. The sampling point is synchro-
nized again with each start bit, so the error accumulates only over the
length of a single word. A receive filter removes spurious pulses of less
than two times the sampling clock period.
The 32-bit, read-only
the write-only
(default), only the lower byte is used—all other bits are zero-filled. How-
ever in pack mode, both the high and low bytes are used. The
are the 9th bit in 9-bit transmission mode. To access
bit in the
LAB UARTxLCR
cleared, writes to this address target the
from this address return the
Because of the destructive nature of reading these registers, shadow
registers are provided for reading the contents of the corresponding
main registers. The shadow registers,
the same contents as the main register, but without changing the
status in any way. These registers are 32-bit registers located at
address 0x3C08 (for
11-6
HIGHER BYTE
23
register is mapped to the same address as
UARTxRBR
and
UARTxTHR UARTxDLL
register must be cleared. When the
UARTxRBR
UART0RBRSH
ADSP-21368 SHARC Processor Hardware Reference
ZERO-FILLED RX9D0
15 9 8
registers. In no pack mode
UARTxRBR
register, while reads
UARTxTHR
register.
UARTxRBRSH
) and 0x4008 (for
LOWER BYTE
7
bits
RX9Dx
, the
UARTD-
bit is
UARTDLAB
, return exactly
).
UART1RBRSH
0