Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 437

6. Set the
to
HIGH
to low to unmask the interrupt. Set bit 8 of the
ister (
IDP_FIFO_GTN_INT
low priority core interrupt when the number of words in the FIFO
is greater than the value of N set.
7. Enable the PDAP by setting the
IDP_PP_CTL
8. Enable the IDP by setting the
IDP_CTL0
Do not set the
this enables DMA transfers.
Core Transfer Notes
The following items provide general information about interrupt-driven
transfers.
• The three LSBs of FIFO data are the encoded channel number.
These are transferred "as is" for this mode. These bits can be used
by software to decode the source of data.
• The number of data samples in the FIFO at any time is reflected in
the
IDP_FIFOSZ
which tracks the number of samples in FIFO.
When using the interrupt scheme, the
the
IDP_CTL0
from the FIFO in the interrupt service routine (ISR).
• If the
IDP_BHD
attempts to read more data than is available in the FIFO results in a
core hang.
ADSP-21368 SHARC Processor Hardware Reference
IDP_FIFO_GTN_INT
and set the corresponding bit in the
) as needed to generate a high priority or
register), if required.
register) and the
IDP_DMA_EN
bit field (bits 31–28 in the
register) can be set to N, so N + 1 data can be read
bit (bit 4 in the
bit (bit 8 of the
DAI_IRPTL_RE
DAI_IRPTL_FE
IDP_PDAP_EN
bit (bit 7 in the
IDP_ENABLE
bits in the
IDP_ENx
bit (bit 5 of the
IDP_CTL0
DAI_STAT
IDP_NSET
register) is not set,
IDP_CTL0
Input Data Port
register)
register
reg-
DAI_IRPTL_PRI
bit (bit 31 in the
register.
IDP_CTL1
register) as
register),
bits (bits 3–0 of
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