Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 350

SPORT Control Registers and Data Buffers
transmitters. The divisor is a 15-bit value, allowing a wide range of serial
clock rates. Use the following equation to calculate the serial clock
frequency:
The maximum serial clock frequency is equal to one-eighth the processor's
internal clock (
Use the following equation to determine the value of
frequency and desired serial clock frequency:
CCLK
DIV0 (0xC02)
DIV1 (0xC03)
DIV2 (0x402)
DIV3 (0x403)
DIV4 (0x4802)
DIV5 (0x4803)
CLKDIV
Clock Divisor
Figure 5-10. DIVx Register
The bit field specifies how many transmit or receive clock cycles are
FSDIV
counted before a frame sync pulse is generated. In this way, a frame sync
can initiate periodic transfers. The counting of serial clock cycles applies
to internally- or externally-generated serial clocks. The formula for the
number of cycles between frame sync pulses is:
# of serial clocks between frame syncs = FSDIV + 1
5-70
f
SPORTx_CLK
) frequency, which occurs when
CCLK
--------------------------------- - 1
=
CLKDIV
8 f
31 30 29 28 27 26 25
0 0 0 0 0 0 0
15 14 13 12 11 10 9
0 0 0 0 0 0 0
ADSP-21368 SHARC Processor Hardware Reference
f CCLK
---------------------------------------
=
( )
+
8 CLKDIV 1
f
CCLK
–
( )
SPORTx_CLK
24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
is set to zero.
CLKDIV
, given the
CLKDIV
0 0
FSDIV
Frame Sync Divisor
0
0
Reserved