Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 461

Pulse Width Modulation
PWMPERIOD _ PWMPERIOD PWMPERI OD
+ +
2 2 2
0 0
count
PWMCHA
PWMCHA
pwm_ ah
pwm_a l
PWMSYNCWT + 1
2xPWMDT 2xPWMDT
pw m_pwm sync_out
PWMP HASE
PWMPERIOD PWMPERIOD
Figure 8-2. Center-Aligned Paired PWM in Single-Update Mode,
Low Polarity
The resulting on-times (active low) of the PWM signals over the full
PWM period (two half periods) produced by the PWM timing unit and
illustrated in Figure 8-3 on page 8-11 may be written as:
The range of T is:
AH
[ × × ]
–
0 2 PWMPERIOD t
PCLK
and the corresponding duty cycles are:
( × ( ) ×
= – +
t
2
T PWMPERIOD PWMCHA PWMDT
PCLK
AH
ADSP-21368 SHARC Processor Hardware Reference 8-9