Dma Control Registers - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

UART Control and Status Registers
DMA Control Registers (UARTxTXCTL, UARTxRXCTL)
Use these registers (described in
DMA, DMA chaining, and to clear the transmit and receive buffers. The
transmit and receive registers are read-write registers and their addresses
are:
UART0TXCTL – 0x3F04
UART1TXCTL – 0x4304
UART0RXCTL – 0x3E04
UART1RXCTL – 0x4204
Table A-49. UARTxTXCTL Register Descriptions
Bit Name
0 UARTEN
1 UARTDEN
2 UARTCHEN
Table A-50. UARTxRXCTL Register Descriptions
Bit Name
0 UARTEN
1 UARTDEN
2 UARTCHEN
A-128
Table A-49
Description
DMA Transmit Buffer Enable. When set (=1), enables the
transmit buffer. When cleared, clears the transmit buffer.
DMA Enable. When set (=1), enables DMA on the speci-
fied channel. When cleared, disables DMA.
Chain Pointer DMA Enable. When set (=1), enables chain
pointer DMA on the specified channel. When cleared, dis-
ables chained DMA.
Description
DMA Receive Buffer Enable. When set (=1), enables the
receive buffer. When cleared, clears the receive buffer.
DMA Enable. When set (=1), enables DMA on the speci-
fied channel. When cleared, disables DMA.
Chain Pointer DMA Enable. When set (=1), enables chain
pointer DMA on the specified channel. When cleared, dis-
ables chained DMA.
ADSP-21368 SHARC Processor Hardware Reference
and Table A-50) to enable