Table 4-14. SPI Pin Enable Selections
Mode
0
1
2
3
As an example, the output of the clock to DPI pin 3 would be configured
in SPI mode 3 as follows.
SRU(SPI_CLK_O,DPI_PB03_I);
SRU(SPI_CLK_O,DPI_PBEN03_I);
Configuring the Two Wire Interface
Each TWI device, whether master or slave, responds to the other devices
with an acknowledge bit when data is received. For details, see
Chapter 12, Two Wire Interface
SRU must be set up so that data communication is possible in both direc-
tions on the data pin.
The examples in
for different TWI modes.
Listing 4-1. TWI Master Transmit Mode
SRU(LOW,DPI_PB11_I)
SRU(TWI_DATA_PBEN_O,DPI_PBEN11_I)
ADSP-21368 SHARC Processor Hardware Reference
Digital Audio/Digital Peripheral Interfaces
CLKPL
CPHASE
0
0
0
1
1
0
1
1
Controller. For proper operation, the
Listing 4-1
through
/* Since TWI output is an open-drain
output, the TWI pin is connected
to logic level low */
Use Pin Enable...
HIGH
HIGH
SPI_CLK_O
SPI_CLK_O
Listing 4-4
show the SRU settings
/* TWI data output connected
to DPI pin 11 input */
4-73
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