Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 581

PCG Setup for I
This example shows how to set up two precision clock generators using
the S/PDIF receiver and an asynchronous sample rate converter (SRC) to
interface to an external audio DAC. In this example an input clock
( ) of 33.330 MHz is assumed and the PCG is configured to provide
CLKIN
a fixed SRC/DAC output sample rate of 65.098 kHz. The input to the
S/PDIF receiver is typically 44.1 kHz if supplied by a CD player but can
also be from another source at any nominal sample rate from about 22
kHz to 192 kHz.
Three synchronous clocks are required: a framesync
clock (
PCGx_CLK
each PCG has only two outputs, this example requires two PCGs. Fur-
thermore, because the digital audio interface requires a fixed-phase
relation between
PCG while the master clock comes from the other.
The = 33.330 MHz is divided by the two PCGs to provide the three
CLKIN
synchronous clocks —
nal DAC. These divisors are stored in 20-bit fields in the
registers. For more information, see "Precision Clock Generator Registers"
on page A-155.
The integer divisors for several possible sample rates based on 33.330
MHz are shown in
CLKIN
ADSP-21368 SHARC Processor Hardware Reference
2
S or Left-Justified DAI
; 256 × FS), and a serial bit clock (
and , these two outputs should come from one
SCLK FSYNC
,
PCGx_CLK SCLK
Table 13-2.
Precision Clock Generators
(FSYNC
; 64 × FS). Since
SCLK
, and for the SRCs and exter-
FSYNC
; FS), a master
PCG_CTL
13-15