Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 711

Table A-15. SPIDMAC, SPIDMACB Register Bit Descriptions
Bit Name
0 SPIDEN
1 SPIRCV
2 INTEN
3 Reserved
4 SPICHEN
6–5 Reserved
7 FIFOFLSH
8 INTERR
9 SPIOVF
10 SPIUNF
11 SPIMME
ADSP-21368 SHARC Processor Hardware Reference
Description
DMA Enable.
0 = Disable
1 = Enable
DMA Write/Read.
0 = Memory write (SPI transmit)
1 = Memory read (SPI receive)
Enable DMA Interrupt on Transfer.
0 = Disable
1 = Enable
SPI DMA Chaining Enable.
0 = Disable
1 = Enable
DMA FIFO Clear.
0 = Disable
1 = Enable
Enable Interrupt on Error.
0 = Disable
1 = Enable
Receive OverFlow Error (SPIRCV = 1).
0 = Successful transfer
1 = Error – data received with RXSPI full
Transmit Underflow Error (SPIRCV = 0).
0 = Successful transfer
1 = Error occurred in transmission with no new data in
TXSPI.
Multimaster Error.
0 = Successful transfer
1 = Error during transfer
Register Reference
A-63