Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 858

Index
AMI bits
ACK pin enable (ACKEN),
AMI enable (AMIEN),
buffer flush (FLSH),
bus hold cycle (HC),
bus idle cycle (HC),
disable packing (PKDIS),
external bus data width (BW),
most significant word first (MSWF),
A-18
predictive read disable (NO_OPT),
read hold cycle (RHC),
wait state enable (WS),
AND breakpoints (ANDBKP) bit,
AND, logical, 2-43, 14-3,
architecture
I/O processor, 2-25
PWM, 8-2
SPDIF transmitter, 9-8
SPORT, 5-8
TWI controller, 12-3
asynchronous access mode (external
memory), 3-81
asynchronous memory interface. See AMI
asynchronous serial communications
(UART), 11-2
audience, intended, xxxi
autobaud detection, 11-1
B
bandwidth in the I/O processor,
bank
internal memory, 3-33
SDRAM address mapping,
bank activate command,
bank column address width, setting,
baud rate, 6-30, 14-49
setting, 2-43, 6-10
I-2
A-18
A-18
A-19
A-18
A-19
A-18
A-18
A-19
A-19
A-18
A-178
A-178
2-12
3-51 to 3-57
3-31
3-42
ADSP-21368 SHARC Processor Hardware Reference
baud rate
SPIBAUD (serial peripheral interface
baud rate) register, 6-5,
UART, 11-4, 11-5, 11-12
beginning and ending an SPI transfer,
BHD (buffer hang disable) bit, 5-64,
BI (break interrupt) bit,
bidirectional connections through the
signal routing unit,
bidirectional functions (transmit, receive),
5-1
biphase
encoded audio stream,
encoded data register (SPDIF_RX_I),
9-18
encoding, 9-11
bits
See also peripheral specific bits
circular buffer x overflow interrupt
(CBxI), B-17, B-21,
emulator lower priority interrupt
(EMUI), B-14, B-18, B-19, B-21,
B-23, B-26
timer expired high priority (TMZHI),
B-15, B-19, B-23
timer expired low priority (TMZLI),
B-17, B-21, B-25
block diagram
I/O processor, 2-25
input data port, 7-2
PWM, 8-2
SPDIF transmitter, 9-8
SPORT, 5-8
SRC, 10-9
TWI controller, 12-3
boolean operator
AND, 2-43, 14-3, A-178
OR, 7-30, 9-24, A-175, A-177,
boot memory select (BMS) pin, 3-30,
14-39
(continued)
A-60
6-29
5-69
11-4
4-13
9-10
B-25
A-178