8-Bit Receive Fifo Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

bus access times, a double byte transfer data access can be performed. Two
data bytes can be written, effectively filling the transmit FIFO buffer with
a single access.
The data is written in little-endian byte order as shown in
where byte 0 is the first byte to be transferred and byte 1 is the second byte
to be transferred. With each access, the transmit status (
the
TWIFIFOSTAT
FIFO buffer is not empty, the core waits until the FIFO buffer is com-
pletely empty and then completes the write access. All bits in this register
are write-only. This register always reads as 0x00000000.
mation, see "16-Bit Transmit FIFO Register (TXTWI16)" on
page A-153.
UNUSED
31 24 23
Figure 12-2. Little-Endian Byte Order

8-Bit Receive FIFO Register

The TWI 8-bit FIFO receive register (
read from the FIFO buffer. Receive data is read from the corresponding
receive buffer in a first-in, first-out order. Although peripheral bus reads
are 32 bits, a read access to the
data byte from the FIFO buffer. With each access, the receive status
( ) field in the
TWIRXS
formed while the FIFO buffer is empty, the core waits until there is at
least one byte in the receive FIFO buffer and then completes the read
access. All bits in this register are read-only.
"8-Bit Receive FIFO Register (RXTWI8)" on page A-154.
ADSP-21368 SHARC Processor Hardware Reference
register is updated. If an access is performed while the
DATA IN REGISTER
B1
16 15
RXTWI8
register is updated. If an access is per-
TWIFIFOSTAT
Two Wire Interface Controller
TWITXS
UNUSED
8 7
) holds an 8-bit data value
RXTWI8
register can only access one receive
For more information, see
Figure 12-2,
) field in
For more infor-
B0
0
12-9