Processor Pin Descriptions
F LA G S 1 5 - 12
P D A P_ D A T A /C TR L
Figure 14-1. Block Diagram of Data Pin Multiplexing (ADSP-2136x)
14-4
F LA G S3 - 0
P W M 3 - 0
FLA G S 7 - 4
P W M 7 - 4
FLA G S1 1 - 8
P W M 1 1 - 8
PW M 1 5 - 1 2
E P_ D A TA 16 - 3 1
PD A P _ D A TA 1 5 - 0
FLA G S/P W M 1 5 - 0
M TM _ D A TA 1 5 - 0
EP _ D A TA 8 - 1 5
F LA G S 8 - 1 5
EP _ D A TA 7 - 0
FL A G S 7 - 0
ADSP-21368 SHARC Processor Hardware Reference
3 - 0
7 - 4
FLA G S/P W M 15 - 0
1 1 - 8
1 5 - 1 2
3 1
1 5
7
0
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