Sdram Controller Address Mapping; Sdc Operation - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SDRAM Controller

SDRAM Controller Address Mapping

To access SDRAM, the SDC multiplexes the internal 32-bit, non-multi-
plexed address into a row and column address. The row and column
address mappings for 32-bit and 16-bit addresses are shown in
Table 3-25. The row and column addresses are muxed to pins
of the processor. The SDRAM address pin
A14–A0
processor's
SDA10
connected to the processor's
For 2 banked SDRAMs connect

SDC Operation

The AMI normally generates an external memory address, which then
asserts the corresponding
strobes. However these control signals are not used by the SDRAM con-
troller. The internal strobes are used to generate pulsed commands (
, ,
SDCKE SDRAS SDCAS
access to SDRAM is based by mapping
memory select to SDRAM space.
The configuration is programmed in the
troller can hold off the processor core or DMA controller with an
internally connected acknowledge signal, as controlled by refresh, or page
miss latency overhead.
A programmable refresh counter is provided which generates background
auto-refresh cycles at the required refresh rate based on the clock fre-
quency used. The refresh counter period is specified with the
in the SDRAM refresh rate control register
page A-48).
3-58
pin. The SDC bank address pins
and
A[17]
select on the SDRAM, along with
CS
, ) within a truth table
SDWE
ADSP-21368 SHARC Processor Hardware Reference
is connected to the
A10
and
BA[0]
pins.
A[18]
with .
BA A[17]
Table 3-26. The memory
causing an internal
ADDR[27:0]
register. The SDRAM con-
SDCTL
("SPERRCTLx Register" on
, are
BA[1]
and
RD WR
,
MSx
field
SDRRC