Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 513

LRCLK_I
SCLK_I
SDATA_I
SMODE_IN2-0
HARD_MUTE_IN
TDM_OUT
MCLK
Figure 10-4. Sample Rate Converter Block Diagram
The FIFO receives the left and right input data and adjusts the amplitude
of the data for both the soft muting of the SRC and the scaling of the
input data by the sample rate ratio before storing the samples in RAM.
The input data is scaled by the sample rate ratio because as the FIR filter
length of the convolution increases, so does the amplitude of the convolu-
tion output. To keep the output of the FIR filter from saturating, the
input data is scaled down by multiplying it by (f
< f
f
S_OUT S_IN
muting the SRC.
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset to the write address, provided by the f
prevent the RAM read pointer from overlapping the write address. The
offset is selectable by the
(16) is added to the write address pointer when
large offset, (64), is added to the write address pointer when
ADSP-21368 SHARC Processor Hardware Reference
Asynchronous Sample Rate Converter
SERIAL
INPUT
PORT
DE-EMPHASIS1-0
SMODE_OUT1-0
WLENGTH_OUT1-0
21BIT_DITHER
MATCHED_PHASED_MODE
. The FIFO also scales the input data to mute and stop
GRPDLYS
DE-EMPHASIS
FILTER
MUTE_OUT
MUTE_IN
SRC_RATIO14-0
SERIAL
OUTPUT
PORT
S_OUT
S_IN
(group delay select) signal. A small offset
GRPDLYS
SAMPLE
RATE
CONVERTER
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
/f ) when
S_IN
counter, is added to
is high, and a
is
GRPDLYS
10-9