Spi General Operations - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SPI General Operations

MICROCONTROLLER
Figure 6-4. SHARC Processor as SPI Master and Slave
SPI General Operations
The SPI in the ADSP-21367/8/9 and ADSP-2137x processors can be used
in a single master as well as in a multimaster environment. In both of
these configurations, every
wise, every
MISO
pin is connected. SPI transmission and reception are always enabled
simultaneously, unless broadcast mode has been selected. In broadcast
mode, several slaves can be configured to receive from the master, but only
one of the slaves can be in transmit mode. This is done by driving the
line, to communicate back with the master. If the transmit or receive is
not needed,
MISO
section describes the clock signals, SPI operation as a master and as a slave,
and error generation conditions.
6-8
SHARC Processor as SPI Slave
8-bit Host
SCLK
S_SEL
MOSI
MISO
SHARC Processor as SPI Master
ADSP-213xx
MASTER DEVICE
SPICLK
FLAG0
MOSI
pin in the SPI system is connected. Like-
MOSI
pin in the system is on a single node, and every
can be ignored and does not need to be connected. This
ADSP-21368 SHARC Processor Hardware Reference
ADSP-213xx
SPI SLAVE DEVICE
SPICLK
SPIDS
MOSI
MISO
AD1855
STEREO 96 KHz DAC
CCLK
CLATCH
DATA
SPICLK
MISO