Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 6

Contents
EMI Registers and Signals ..................................................... 3-16
External Port Arbitration Logic ......................................... 3-18
Channel Freezing .............................................................. 3-18
Managing Data Paths ........................................................ 3-18
External Memory Interface Pins ............................................ 3-19
Asynchronous Memory Interface ................................................. 3-20
AMI Timing Control .................................................................. 3-21
Wait States ............................................................................ 3-21
Bus Idle Cycles ...................................................................... 3-22
Bus Hold Cycles .................................................................... 3-23
Setting AMI Modes .................................................................... 3-24
External Memory Reads ........................................................ 3-25
Data Packing .................................................................... 3-25
External Memory Writes ....................................................... 3-26
Data Packing .................................................................... 3-27
Read/Write Throughput ........................................................ 3-28
External Access Addressing .................................................... 3-28
External Port DMA ............................................................... 3-30
Booting Through the AMI .................................................... 3-30
SDRAM Controller .................................................................... 3-30
Definition of Terms .............................................................. 3-31
Timing External Memory Accesses ......................................... 3-36
Parallel Connection of SDRAMs ........................................... 3-39
SDRAM Control Register (SDCTL) ...................................... 3-39
vi ADSP-21368 SHARC Processor Hardware Reference