Uartxier Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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UARTxIER Register

The UART interrupt enable registers (

requests for system handling of empty or full states of UART data regis-

ters. Unless polling is used as a means of action, the

bits in this register are normally set.

Setting these registers without enabling system DMA causes the UART to

notify the processor of the state of the data inventory by means of inter-

rupts. For proper operation in this mode, system interrupts must be

enabled, and appropriate interrupt handling routines must be present. For

backward compatibility, the

interrupt status.

With system DMA enabled, the UART uses DMA to transfer data to or

from the processor. Dedicated DMA channels are available to receive and

transmit operations. Line error handling can be configured completely

independently from the receive/transmit setup.

ister. To access the

The UART interrupts are all combined into the digital peripheral inter-

face (DPI) interrupt. The

interrupt is for the transmitter or receiver. For DMA, the transmit inter-

rupt is generated when a DMA in transmit mode is complete whereas the

receive interrupt is generated when receive DMA is complete or when a

receive error occurs. The

rupt is due to DMA completion or errors.

The UART receive and transmit interrupt can also be programmed

through the peripheral interrupt control registers (

rupts for DMA. (By default, these interrupts are not configured in the

them.) For I/O mode, both the transmit and receive interrupt can be

ADSP-21368 SHARC Processor Hardware Reference

UART Port Controller

) are used to enable

registers still reflect the correct

) as separate inter-

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