Sru1 Programming For Input And Output Streams; Control Register Programming And Enable; S/Pdif Receiver Programming Guidelines; Control Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SRU1 Programming for Input and Output Streams

Signal routing unit 1 (SRU1) is used to connect the S/PDIF transmitter
bi-phase data out to the output pins or to the S/PDIF receiver. The serial
data input and the over sampling clock input also needs to be routed
through SRU1. See
Clock Signals" on page 4-19
on page 4-25.

Control Register Programming and Enable

After SRU1 programming is complete, if the channel status or validity
buffer needs enabling, write to the buffers first with the required data and
then enable the buffers using the
Also write other control values such as
enable the transmitter by setting the

S/PDIF Receiver Programming Guidelines

The following guidelines are intended to help in programming the
S/PDIF receiver.

Control Register

The S/PDIF receiver is enabled at default to receive in two channel mode.
Therefore, if the receiver is not used, programs should disable the digital
PLL to avoid unnecessary switching. This is accomplished by writing into
the
DIR_PLLDIS
S/PDIF receiver is used, this register does not need to be changed. For a
detailed description of this register, see
(DIRCTL)" on page
The register contains control parameters for the S/PDIF receiver.
DIRCTL
The control parameters include mute information, error controls, SCDF
mode select and enable, and digital PLL disable.
ADSP-21368 SHARC Processor Hardware Reference
For more information, see "Group A Connections—
and "Group B Connections—Data Signals"
DIT_CHANBUF
bit (bit 7) in the
DIRCTL
A-92.
S/PDIF Transmitter/Receiver
bit in the
, and
DIT_SMODEIN
bit.
DIT_EN
register. In most cases, when the
"Receiver Control Register
register.
DITCTL
and
DIT_FREQ
9-25