Managing Dma Channel Priority - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

transfers. Table 2-5
register assignments for the ADSP-21367/8/9 and ADSP-2137x
processors.
DMA channels vary by processor model. For a breakdown of DMA
channels for a particular model, see the processor specific data
sheet.

Managing DMA Channel Priority

The DMA channel prioritization scheme ranks channel 0 as highest prior-
ity and channel 34 as the lowest priority.
DMA channels in priority order. When a channel becomes the highest
priority requester, the I/O processor services the channel's request. In the
next clock cycle, the I/O processor starts the DMA transfer.
The I/O data (IOD) bus is 32 bits wide and is the only path that the IOP
uses to transfer data between internal memory and the peripherals. When
there are two or more peripherals with active DMAs in progress, they may
all require data to be moved to or from memory in the same cycle. For
example, the input data port may fill its
a word into its
the DMA channels for each of the processor's I/O ports negotiate channel
priority with the I/O processor using an internal DMA request/grant
handshake.
Each I/O port has one or more DMA channels, and each channel has a
single request and a single grant. When a particular channel needs to read
or write data to internal memory, the channel asserts an internal DMA
request. The I/O processor prioritizes the request with all other valid
DMA requests. When a channel becomes the highest priority requester,
the I/O processor asserts the channel's internal DMA grant. In the next
clock cycle, the DMA transfer starts.
paths for internal DMA requests within the I/O processor.
ADSP-21368 SHARC Processor Hardware Reference
shows the DMA channel allocation and parameter
buffer. To determine which word is transferred first,
RXn
Table 2-7 on page 2-32
buffer just as a SPORT shifts
RXPP
Figure 2-3 on page 2-30
I/O Processor
lists the
shows the
2-19