Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 400

SPI Transfer Formats
When
CPHASE
between each word in the transfer. When
remain active (
Figure 6-5 shows the SPI transfer protocol for
starts toggling in the middle of the data transfer,
SPICLK
= 1.
MSBF
CLOCK CYCLE
NUMBER
SPICLK
CLKPL=0
(SPI MODE 0)
SPICLK
CLKPL=1
(SPI MODE 2)
MOSI
FROM MASTER
*
MISO
FROM SLAVE
MSB
SPIDS
FROM MASTER
Figure 6-5. SPI Transfer Protocol for CPHASE = 0
Figure 6-6 shows the SPI transfer protocol for
starts toggling at the beginning of the data transfer,
SPICLK
= 1.
MSBF
6-28
= 0, the slave select line,
) between successive transfers or be inactive (
LOW
1 2 3
MSB 6 5
6 5
ADSP-21368 SHARC Processor Hardware Reference
, must be inactive (
SPIDS
= 1,
CPHASE
CPHASE
4 5 6
4 3 2
4 3 2
CPHASE
)
HIGH
may either
SPIDS
).
HIGH
= 0. Note that
= 0, and
WL
7 8
1 LSB *
1 LSB *
* = UNDEFINED
= 1. Note that
= 0, and
WL