Receive/Transmit Repeated Start Sequence - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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• Re-program

This interrupt is generated due to the arrival of a byte into the

receive FIFO. Simple data handling is all that is required.

Receive/Transmit Repeated Start Sequence

illustrates a repeated start data receive followed by a data

transmit sequence. The shading in the figure indicates the slave has the

7-BIT ADDRESS

SHADING INDICATES

SLAVE HAS THE BUS

Figure 12-9. Receive/Transmit Data Repeated Start

The tasks performed at each interrupt are:

This interrupt is generated due to the arrival of one or two data

bytes into the receive FIFO. The

time (or earlier) and

direction of the next transfer. The

before the addressing phase of the subsequent transfer begins.

ADSP-21368 SHARC Processor Hardware Reference

with the desired number of bytes to

TWIRXINT INTERRUPT

TWIMCOM INTERRUPT

should be cleared to reflect the change in

Two Wire Interface Controller

7-BIT ADDRESS

TWITXINT INTERRUPT

bit should be set at this

bit must be cleared

TWIMCOM INTERRUPT

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