Contents
Status Bits ........................................................................ 9-26
Conceptual Model ................................................................ 10-4
Hardware Model ................................................................... 10-7
Group Delay ....................................................................... 10-12
SRC Operation ......................................................................... 10-12
Enabling the SRC ............................................................... 10-13
Serial Data Ports ................................................................. 10-13
Data Format ................................................................... 10-13
TDM Input Mode .......................................................... 10-16
Bypass Mode .................................................................. 10-18
Mute Control ..................................................................... 10-19
Soft Mute ....................................................................... 10-20
Hard Mute ..................................................................... 10-20
Auto Mute ...................................................................... 10-20
SRC Registers ........................................................................... 10-21
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ADSP-21368 SHARC Processor Hardware Reference
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