Tdm Input Mode; Matched-Phase Mode - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

SRC Operation

TDM Input Mode

In TDM input mode, several SRCs can be daisy-chained together and
connected to the serial input port of an ADSP-21367/8/9 and
ADSP-2137x processor or other processor
tains a 64-bit parallel load shift register. When the
each SRC parallel loads its left and right data into the 64-bit shift register.
The input to the shift register is connected to the
output is connected to the
to the signal of the next SRC, a large shift register is created, which
TDM_I
is clocked by the
The number of SRCs that can be daisy-chained together is limited by the
maximum frequency of the
example, if the output sample rate, f
be connected since 512 × f
ADSP-2136x
DR0
TFS0
TCLK0
Figure 10-7. TDM Input Mode

Matched-Phase Mode

The matched-phase mode is the mode discussed in
on page 10-2. This mode eliminates the phase mismatch between multiple
SRCs. The master SRC device transmits its f
the pin to the slave SRC's
SDATA_O
the transmitted f
ratio instead of their own internally-derived f
10-16
signal. By connecting the
TDM_I
signal.
SCLK_I
SCLK_O
is less than 25 MHz.
S
SRCx
TDM_OUT
SDATA_I
LRCLK_I
SCLK_I
/f ratio and use the transmitted f
S_OUT S_IN
ADSP-21368 SHARC Processor Hardware Reference
(Figure 10-7). The SRC con-
LRCLK_I
SDATA_IN
signal, which is about 25 MHz. For
, is 48 kHz, up to eight SRCs could
S
SRCx
SDATA_I TDM_OUT
LRCLK_I
SCLK_I
"Theory of Operation"
/f
S_OUT S_IN
pins. The slave SRCs receive
TDM_IN
/f
S_OUT
pulse arrives,
, while the
signal
SDATA_I
LRCLK
SCLK
SRCx
SDATA_I
LRCLK_I
SCLK_I
ratio through
/f
S_OUT S_IN
ratio as shown
S_IN
TDM_OUT