Interrupt And Timer Pins; Core-Based Flag Pins - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Processor Pin Descriptions
• pin is not used
DATA9
• pin acts as
DATA8

Interrupt and Timer Pins

The processor's external interrupt pins, flag pins, and timer pin can be
used to send and receive control signals to and from other devices in the
system. The
IRQ2–0
pin is mapped on the
received on the
require the processor to perform some task on demand. A
memory-mapped peripheral, for example, can use an interrupt to alert the
processor that it has data available.
Appendix B, Interrupts..
The output is generated by the on-chip timer. It indicates to other
TIMEXP
devices that the programmed time period has expired. For more informa-
tion, see the ADSP-2136x SHARC Processor Programming Reference.

Core-Based Flag Pins

The pins allow single bit signalling between the processor and
FLAG3–0
other devices. For example, the processor can raise an output flag to inter-
rupt a host processor. Each flag pin can be programmed to be either an
input or output. In addition, many processor instructions can be condi-
tioned on a flag's input value, enabling efficient communication and
synchronization between multiple processors or other interfaces.
The flags are bidirectional pins and all have the same functionality. The
bits in the
FLGxO
more information, see the ADSP-2136x SHARC Processor Programming
Reference.
14-8
PDAP STROBE
pins are mapped on the
pin. Hardware interrupt signals (
FLAG3
pins. Interrupts can come from devices that
FLAG2–0
register program the direction of each flag pin. For
FLAGS
ADSP-21368 SHARC Processor Hardware Reference
(output)
pins and the
FLAG2–0
For more information, see
TIMEXP
) are
IRQ2–0