Beginning And Ending An Spi Transfer - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

CLO CK CYCLE
NUMBE R
SP ICLK
CLKPL=0
(SP I MODE 1 )
SP ICLK
CLKPL=1
(SP I MODE 3 )
MOSI
FROM MASTE R
*
MISO
FROM SLAVE
*
SP IDS
TO SLAVE
Figure 6-6. SPI Transfer Protocol for CPHASE = 1

Beginning and Ending an SPI Transfer

An SPI transfer's defined start and end depend on: whether the device is
configured as a master or a slave, whether
which transfer initiation mode (
= 0, a transfer starts when either the
CPHASE
register is read, depending on the
RXSPI
the transfer, the enabled slave-select outputs are driven active (
ever, the
SPICLK
period. For a slave with
input transitions to low.
For = 1, a transfer starts with the first active edge of
CPHASE
both slave and master devices. For a master device, a transfer is considered
complete after it sends and simultaneously receives the last data bit. A
transfer for a slave device is complete after the last sampling edge of
.
SPICLK
ADSP-21368 SHARC Processor Hardware Reference
1 2 3
MS B 6
5
MS B 6 5
TIMOD
starts toggling after a delay equal to one-half the
= 0, the transfer starts as soon as the
CPHASE
Serial Peripheral Interface Ports
4 5 6
4 3 2
4 3 2
mode is selected, and
CPHASE
) is selected. For a master SPI with
register is written or the
TXSPI
selection. At the start of
TIMOD
7 8
1 LSB *
1 LSB
* = UNDEF INED
). How-
LOW
SPICLK
SPIDS
for
SPICLK
6-29