Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 807

PCG_PW (0x24C4)
PCG_PW2 (0x24CA)
Reserved
INVFSB
Active Low Frame Sync B/D
Reserved
INVFSA
Active Low Frame Sync A/C
Figure A-76. PCG_PWx Registers (in Bypass Mode)
Table A-66. PCG_PWx Register Bit Descriptions
(in Bypass Mode)
Bit
0
1
15–2
16
17
31–18
ADSP-21368 SHARC Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9
0 0 0 0 0 0 0
Name Description
STROBEx One Shot Frame Sync A/C. Frame sync is a pulse with dura-
tion equal to one period of the MISCA2_I signal repeating at
the beginning of every frame.
Note: This is valid in bypass mode only.
INVFSx Active Low Frame Sync Select for Frame Sync A/C.
0 = Active high frame sync
1 = Active low frame sync
Reserved (In bypass mode, bits 15-2 are ignored.)
STROBEx One Shot Frame Sync B/D. Frame sync is a pulse with dura-
tion equal to one period of the MISCA3_I signal repeating at
the beginning of every frame.
Note: This is valid in bypass mode only
INVFSx Active Low Frame Sync Select.
0 = Active high frame sync
1 = Active low frame sync
Reserved (In bypass mode, bits 31–18 are ignored.)
Register Reference
0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
0 0
STROBEB
One Shot Frame
Sync B/D
0
0
STROBEA
One Shot Frame
Sync A/C
A-159