Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 880

Index
S/PDIF registers
extracted receiver frame sync output
(SPDIF_RX_FS_O),
extracted receiver sample clock output
(SPDIF_RX_CLK_O),
receive control (DIRCTL),
receiver status (DIRSTAT),
receiver TDM output
(SPDIF_RX_TDMCLK_O),
right channel status for subframe A
(DIRCHANL), A-96
right channel status for subframe B
(DIRCHANR), A-96
right channel transmit status
(DITCHANR), 9-12
transmit control (DITCTL), 9-12, 9-17,
A-86
transmit status (DITCHANL) left
channel, 9-12
user bit buffer (DITUSRBITAx),
sampling clock period, UART,
sampling point, UART,
SB (UART set break) bit, 11-3,
SCHEN_A and SCHEN_B (serial port
chaining enable) bit, 5-63,
SDEN (serial port DMA enable) bit, 2-48,
5-63, A-38
SDRAM
buffered system, 3-46,
bus errors, 3-71
core address mapping,
errors, 3-77
page size, 3-34
refresh rate, 3-50
restrictions, 3-52
SDRAM bits
burst stop (NOBSTOP),
CAS latency (SDCL),
column address width (SDCAW),
I-24
(continued)
9-18
9-18
9-12
A-94
9-19
9-12
11-6
11-6
A-118
A-38
3-47
3-52
A-25
A-22
A-23
ADSP-21368 SHARC Processor Hardware Reference
SDRAM bits
disable clock and control (DSDCTL),
A-22
external data path width (X16DE),
force auto refresh (Force AR),
force load mode register write (Force
LMR), A-24
force precharge (Force PC),
optimization (SDROPT),
optional refresh (SDORF),
page size is 128 words (PGSZ 128),
pipeline option with external register
buffer (SDBUF),
power-up mode (SDPM),
power-up sequence start (SDPSS),
predictive addressing (SDMODIFY),
A-27
RAS setting (SDTRAS),
RDC setting (SDTRCD),
refresh delay (RDIV),
row address width (SDRAW),
RP setting (SDTRP),
self-refresh enable (SDSRF),
WR setting (SDTWR),
SDRAM controller, 3-30
address space, external memory,
addressing (16-bit), 3-55
addressing (32-bit), 3-53
bank activate, 3-36
burst disable, A-25
burst length definition,
burst type, 3-32
calculating refresh rate,
CAS latency, 3-32
CAS latency (SDCL) bit,
CBR (CAS before RAS),
clock frequencies, 3-37
configuring, 3-62
control (SDCTL) register,
data mask, 3-33
(continued)
A-24
A-24
A-24
A-27
A-24
A-25
A-24
A-23
A-23
A-23
A-24
A-27
A-25
A-23
A-23
A-24
3-52
to 3-57
to 3-54
3-32
3-50
3-37
3-33
3-39