Pwm Output Disable Registers (Pwmsegx - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Pulse Width Modulation Registers

PWM Output Disable Registers (PWMSEGx)

These 16-bit read/write registers, described in
output signals of the four PWM groups. The addresses for these registers
are:
PWMSEG0 — 0x3008
PWMSEG1 — 0x3018
PWMSEG2 — 0x3408
PWMSEG3 — 0x3418
Table A-28. PWMSEGx Register Bit Descriptions
Bit Name
0 PWM_BH
1 PWM_BL
2 PWM_AH
3 PWM_AL
A-82
Description
Channel B High Disable. Enables or disables the channel B
output signal.
0 = Enable
1 = Disable
Channel B Low Disable. Enables or disables the channel B out-
put signal.
0 = Enable
1 = Disable
Channel A High Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable
Channel A Low Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable
ADSP-21368 SHARC Processor Hardware Reference
Table A-28, control the