Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 521

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10-8. The master device can have both its serial ports in slave

mode as depicted, or either one in master mode. The slave SRCs must

signals may be asynchronous with respect to each other in this mode.

There must be 32

The SRC supports the matched-phase mode for all serial output data for-

mats: left-justified, I

LRCLKI (FS_IN)

PHASE-MASTER

Figure 10-8. Typical Configuration for Matched-Phase Mode Operation

Note that in the left-justified, I

of each channel subframe are used to transmit the matched-phase data. In

right-justified mode, the upper eight bits are used to transmit the

matched-phase data. This is shown in

ADSP-21368 SHARC Processor Hardware Reference

Asynchronous Sample Rate Converter

bits set to 1, respectively. The

cycles per subframe in matched-phase mode.

S, right-justified, and TDM mode.

S, and TDM modes, the lower eight bits