Companding - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Linear transfers occur in the primary channel, if the channel is active and
companding is not selected for that channel. Companded transfers occur
if the channel is active and companding is selected for that channel. The
multichannel compand select registers,
receive channels that are companded when multichannel mode is enabled.
For more information, see "SPORT Compand Registers (SPxCCSy)" on
page A-47.
Transmit or receive sign extension is selected by bit 0 of
registers and is common to all transmit or receive channels. If bit 0
SPCTLx
of is set, sign extension occurs on selected channels that do not have
DTYPE
companding selected. If this bit is not set, the word contains zeros in the
MSB positions. Companding is not supported for B channel. For B chan-
nels, transmit or receive sign extension is selected by bit 0 of
registers.
SPCTLx

Companding

Companding (compressing/expanding) is the process of logarithmically
encoding and decoding data to minimize the number of bits that must be
sent. The processor's SPORTs support the two most widely used com-
panding algorithms, A-law and μ-law, performed according to the CCITT
G.711 specification. The type of companding can be selected indepen-
dently for each SPORT. Companding is selected by the
registers.
SPCTLx
Companding is supported on the A channel only. SPORT0, 2, 4
and 6 primary channels are capable of compression, while SPORTs
1, 3, 5 and 7 primary channels are capable of expansion.
In multichannel mode, when companding and expansion is
enabled, the number of channels must be programmed via the
bit in the
The
SPxCSn
writing to transmit FIFO.
ADSP-21368 SHARC Processor Hardware Reference
registers before writing to the transmit FIFO.
SPMCTLx
and registers should also be written before
SPxCCsn
, specify the transmit and
SPxCCSy
DTYPE
DTYPE
Serial Ports
in the
in the
DTYPE
field of the
NCH
5-47