Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 334

SPORT Control Registers and Data Buffers
Table 5-6. SPORT2 and SPORT3 Registers (Cont'd)
Register Function
Name
RX3A Receiver FIFO Register in SP3A
TX3B Transmitter FIFO Register in SP3B
RX3B Receiver FIFO Register in SP3B
Table 5-7. SPORT4 and SPORT5 Registers
Register Function
Name
SPCTL4–5 SPORT Control Register for SPORT4, 5
DIV4–5 Clock and Frame Sync Divisors for
SPORT4, SPORT5
SPMCTL4 SPORT Multichannel Control Register
for SPORT4
SP4CS0–3 Multichannel Active channels select for
SPORT4
SP5CS0–3 Multichannel Active channels select for
SPORT5
SP4CCS0–3 Multichannel Transmit Compand Select
(128 channels) for SPORT4
SP5CCS0–3 Multichannel Receive Compand Select
(128 channels) for SPORT5
SPCNT4–5 Clock and Frame Sync. Divider Counter
(Internal Use Only) for SPORT4,
SPORT5
SPMCTL5 SPORT Multichannel Control Register
for SPORT5
SPERRCTL SPORT Error Interrupt Control Register
4–5 for SPORT4, SPORT5
Reserved
5-54 ADSP-21368 SHARC Processor Hardware Reference
Width No. of Memory Map
Registers [17:0]
32 1 00465
32 1 00466
32 1 00467
Width No. of Memory Map
Registers [17:0]
32 2 00800–00801
32 2 00802–00803
32 1 00804
32 4 00805–00808
32 4 00809–0080C
32 4 0080D–00810
32 4 00811–00814
32 2 00815–00816
32 1 00817
7 2 00818–00819
0081A–0083F