General Call Support; Fast Mode - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Data Transfer Mechanics
• TWI controller addressed as a slave-transmitter
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (
indicates a slave transfer error (
• TWI controller as a master-transmitter or master-receiver
If the stop bit is set during an active master transfer, the TWI con-
troller issues a stop condition as soon as possible to avoid any error
conditions (as if data transfer count had been reached).

General Call Support

The TWI controller always decodes and acknowledges a general call
address if it is enabled as a slave (
( ). General call addressing (0x00) is indicated by the setting of the
TWIGC
bit, and by the nature of the transfer, the TWI controller is a
GCALL
slave-receiver. If the data associated with the transfer is to be not acknowl-
edged (NAKed), the
If the TWI controller is to issue a general call as a master-transmitter, the
appropriate address and transfer direction can be set along with loading
transmit FIFO data.

Fast Mode

Fast mode essentially uses the same mechanics as standard mode. It is the
electrical specifications and timing that are different. When fast mode is
enabled (
TWIFAST
cal requirements.
• Serial data rise times before arbitration evaluation (t
• Stop condition setup time from serial clock to serial data (t
• Bus free time between a stop and start condition (t
12-14
TWISEN
bit can be set.
TWINAK
), the following timings are modified to meet the electri-
ADSP-21368 SHARC Processor Hardware Reference
).
TWISERR
) and if general call is enabled
) and
TWISCOMP
)
r
)
SUSTO
)
BUF