Uart Dma - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

UART DMA

UART DMA
In the UART, separate receive and transmit DMA channels move data
between the UART and memory. The software does not have to move
data, it just has to set up the appropriate transfers either through the
descriptor mechanism or through auto buffer mode. See also
troller Operation" on page
To perform DMA transfers, the UART has a special set of receive and
transmit registers. These registers are listed in
Table 2-13. UART DMA Registers
Register
UARTxRXCTL (3 bits)
IIUARTxRX (19 bits)
IMUARTxRX (16 bits)
CUARTxRX (16 bits)
CPUARTxRX (20 bits)
UARTxRXSTAT (3 bits)
UARTxTXCTL (3 bits)
IIUARTxTX (19 bits)
IMUARTxTX (16 bits)
CUARTxTX (16 bits)
CPUARTxTX (20 bits)
UARTxTXSTAT (3 bits)
No additional buffering is provided in the UART DMA channel, so the
latency requirements are the same as in non-DMA mode. However, the
latency is determined by the bus activity and arbitration mechanism and
not by the processor loading and interrupt priorities.
2-44
2-13.
Description
DMA Config/Control register for UART Rx
Address for DMA
Modifier
Count
Chain Pointer
DMA Status register
DMA Config/Control register for UART Tx
Address for DMA
Modifier
Count
Chain Pointer
DMA Status register
ADSP-21368 SHARC Processor Hardware Reference
"DMA Con-
Table 2-14.