Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 538

UART Control and Status Registers
interrupt priority using the peripheral interrupt priority control registers.
For more information, see "Peripheral Interrupt Priority Control Regis-
ters" on page A-164.
Table 11-1. IIR Register in I/O Mode
Bit Status NINT
000 1
011 0
100 0
010 0
001 0
000 0
When cleared, the pending interrupt bit (
pending. The
STATUS
rupt. The receive line status has the highest priority; the
interrupt has the lowest priority. In the case where both interrupts are sig-
nalling, the
UARTxIIR
When a UART interrupt is pending, the interrupt service routine (ISR)
needs to clear the interrupt latch explicitly. For information on how to
clear the latches see
page A-124.
The transmit interrupt request is cleared by writing new data to the
register or by reading the
TxTHR
role of the
UARTxIIR
not want to transmit further data.
11-10
Interrupt Interrupt Type
Priority
– No interrupt
1 Rx line status
2 Address detect
3 Rx data ready
4 THR empty
5 THR and TSR empty
field indicates the highest priority pending inter-
register reads 0x06.
"Interrupt Identification Registers (UARTxIIR)" on
UARTxIIR
register read in the case where the service routine does
ADSP-21368 SHARC Processor Hardware Reference
Cleared When...
–
LSR is read
RBR is read
RBR is read
Write THR or Read
IIR when priority = 4
Write THR or Read
IIR when priority = 5
) signals that an interrupt is
NINT
UARTTXFI
register. Please note the special
UAR-