Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 879

S/PDIF
serial clock input, 9-24
serial data, 9-10
single-channel, double-frequencey
format, 9-8
SRU control registers, 9-8,
SRU routing, 9-11
stream disconnected
(DIR_NOSTREAM) bit,
subframe format, 9-4
two channel mode, 9-8
S/PDIF bits
biphase error (DIR_BIPHASEERROR),
A-95
buffer enable (DIT_CHANBUF),
channel status buffer enable
(DIT_CHANBUF),
channel status byte 0 A
(DIT_B0CHANL),
channel status byte 0 B
(DIT_B0CHANR),
channel status byte 0 for subframe A
(DIR_B0CHANL),
channel status byte 0 for subframe B
(DIR_B0CHANR),
disable PLL (DIR_PLLDIS),
frequency multiplier (DIT_FREQ),
A-88
lock error (DIR_LOCK),
lock receiver (DIR_LOCK),
non-audio frame mode channel 1 and 2
(DIR_NOAUDIOLR),
non-audio subframe mode channel 1
(DIR_NOAUDIOL),
parity (DIR_PARITYERROR),
parity biphase error (DIR_BIPHASE),
A-93
receive mute (DIR_MUTE),
ADSP-21368 SHARC Processor Hardware Reference
(continued)
9-18
A-95
9-25
A-88
A-89
A-89
A-95
A-95
A-93
A-93
A-95
A-95
A-95
A-95
A-93
S/PDIF bits
select single-channel, double-frequency
mode channel (DIT_SCDF_LR),
A-88
serial data input format
(DIT_SMODEIN),
single channel enable (TX_SCDF_EN),
9-9
single channel enable left right
(TX_SCDF_EN),
single channel left right
(TX_SCDF_LR),
single-channel, double-frequency
channel select (DIR_SCDF_LR),
A-93
single-channel, double-frequency mode
enable (DIR_SCDF),
transmit mute (DIT_MUTE),
transmit single-channel,
double-frequency enable
(DIT_SCDF), A-88
transmitter enable (DIT_EN),
user, 9-9
validity (DIR_VALID),
validity bit A (DIT_VALIDL),
validity bit B (DIT_VALIDR), A-88,
A-89
S/PDIF registers
audio data output
(SPDIF_RX_DAT_O),
bi-phase encoded data (SPDIF_RX_I),
9-18
channal A transmit status
(SPDIF_TX_CHSTA), A-89,
channal B transmit status
(SPDIF_TX_CHSTB),
channel status, 9-12
control (DITCTL),
external frame sync
(SPDIF_EXTPLLCLK_I),
Index
(continued)
A-88
9-9
9-9
A-93
A-87
A-87
A-95
A-88
9-18
A-90
A-90
9-12
9-18
I-23