Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 623

Table 14-6. Clock Relationships
Timing
Requirements
t
CK
t
PLLICK
t
CCLK
t
PCLK
t
SCLK
t
SPICLK
1 where:
SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPICTL register)
SCLK = serial port clock
SPICLK = SPI clock
Table 14-7 describes clock ratio requirements.
ple clock derivation.
Table 14-7. Clock Ratios
Timing
Requirements
c =
RTO
s =
RTO
Table 14-8. Clock Derivation
Timing
Requirements
t
CCLK
t
SCLK
ADSP-21368 SHARC Processor Hardware Reference
1
Description
= CLKOUT Clock Period
= PLL Input Clock
= Core Clock Period (Processor)
Peripheral Clock Period = 2 × t
=
= Serial Port Clock Period = (t
= SPI Clock Period = (t
Description
Core to CLKOUT ratio (3:1, 8:1, or 16:1, determined by CLK_CFGx
pins at reset). Programs can modify this ratio using the PMCTL register.
Sport:core clock ratio (wide range determined by xCLKDIV)
Description
) × cRTO
= (t
CK
) × sRTO
= (t
CCLK
CCLK
) × SR
PCLK
) * SPIR
CCLK
Table 14-8
System Design
shows an exam-
14-31