Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 499

audio sample and slowly and linearly decrementing it to zero, over a
period of 4096 frames. During this time, the PLL three-states the charge
pump until the soft mute has been completed. If non-linear PCM audio
data is in the AES3/SPDIF stream when the
receiver sends out zeros after the last valid sample.
When the
DIR_LOCK
unlocked and the audio data is handled according to the
DIR_NOAUDIO[1:0]
receiver functions as follows.
• 00 = no action is taken with the audio data.
• 01 = the last valid audio sample is held.
• 10 = zeros are sent out after the last valid sample.
• 11 = soft mute of the last valid audio sample is performed (as if
DIR_NOSTREAM
This is valid only when linear PCM audio data is in the stream.
When non-linear audio data is in the stream, this mode defaults to
the case of
When a parity or bi-phase error occurs, the audio data is handled accord-
ing to the
DIR_BIPHASEERROR_CTL[1:0]
• 00 = no action is taken with the audio data.
• 01 = the last valid sample is held.
• 10 = the invalid sample is replaced with zeros.
The ,
VALIDITY
stored in the receiver status register as W1C bits.
ADSP-21368 SHARC Processor Hardware Reference
bit is deasserted, it means that the PLL has become
bits in the
DIRCTL
is asserted).
DIR_NOAUDIO[1:0]
,
NONAUDIO NOSTREAM
S/PDIF Transmitter/Receiver
NOSTREAM
register. When this happens, the
bits = 10.
bits in the following manner.
, , and
BIPHERR PARITY
bit is asserted, the
bits are also
LOCK
9-23